Cortex M4 Firmware

[wild]

I'm just curious.
I have worked on problem like this only on STM32: the analysis of the ST-Link and J-Link Firmware and the software which make the firmware upgrade (DFU like).
In those software (Segger JlinkARM.DLL, STLinkReflash, ...) the firmware is stored without any info "attached" (the flash starting address and blob size are stored in a different structure), since my error interpreting the eychei's BIN file*.
Questions:
- where did you get the 'chunk_t' info?
- is it the standard way of the (I presume) NXP DFU utility?

*) when I wrote my first answer I had no time to look at the memory map of the K10 processors [eychei: take a look at the map, it directly answers your question] especially because I didn't find any reference to MK10DZ processors!!!